1. Field of the Invention
This invention relates to improvements in integrated circuit isolation techniques and apparatus and, more specifically, to improvements in apparatus and methods for galvanically isolating two circuits, such as integrated circuits or the like, from each other.
2. Brief Description of the Prior Art
In many circuit constructions, it is often necessary to provide dc isolation between two or more integrated circuits. For example, the ground potential of one integrated circuit may be at a different dc level from the ground potential of another integrated circuit to which it may be connected. In such cases, without isolation, there could be an effective short circuit between the two integrated circuits. Accordingly, in such cases, ground potential isolation is required and many such prior art isolation schemes are known, one of which is described by IEEE 1394-1995, Annex J which is an IEEE standard. In the prior art, however, when isolated ground design circuits such as specified by IEEE 1394-1995 have been required, the isolation scheme between the physical layer device and the link layer device suggested in the IEEE standard is costly in terms of external components required, board space, supply current and silicon area. These prior art current isolation schemes also have poor noise margin or propagation delay.
More particularly, one of the problems with the prior art techniques of providing isolation between two integrated circuit devices is the large number of components required to effect the dc isolation between pins. For example, the IEEE 1394-1995 standard requires, in its capacitor embodiment, two relatively large-sized capacitors and seven resistors external to the device as well as specific differentiating tristating and hysteresis input buffer circuitry on the device. Therefore, it can be seen that when the required isolation circuitry is employed over a number of interconnections for every pin on each integrated circuit that is interconnected, a large number of such isolation circuits will be required. Moreover, depending upon the voltages that are to be handled by the capacitors, for example, 50 volts or less, relatively large size capacitors are required which consume even more space on the board through which the interconnect is accomplished. Furthermore, it will be appreciated that accompanying the large number of components required to accomplish the integrated circuit interface and isolation is a concomitant increase in the cost of the final product.
The IEEE 1394-1995 standard additionally has an isolation circuit embodiment that is implemented with a transformer. The transformer isolation circuit embodiment also requires a large number of components, but can be constructed to withstand higher dc voltages than the capacitor embodiment, for example, up to about 500 volts. Again, the transformer embodiment requires a significant amount of interconnect physical area in which to construct the isolation circuit and, when multiplied by the number of pins that are interconnected, a significant number of circuit components and amount of layout area is consumed.
In typical operation of a circuit that is interconnected using isolation circuitry of the type generally used in accordance with the IEEE 1394-1995 standard to enable bi-directional signals to be delivered to and supplied from the integrated circuit, a differentiating output buffer circuit and a digital input buffer having signal hysteresis are provided. The output buffer and input buffer are generally connected to the same input/output pin to achieve bi-directional signal transfer. The output buffer circuit is generally clocked by clock pulse sources onboard the integrated circuit device on which the output buffer is constructed.
Differentiation circuits of the type provided as a part of the input buffer circuit are difficult and complex to construct in an integrated circuit structure and, additionally, require considerable chip area on the integrated circuit device. When the number of input/output pins is increased, an increased amount of chip area is required to provide the multiplied number of differentiating circuits for each input buffer section.
Moreover, a differentiation input buffer circuit typically has an amplifier having hysteresis. The hysteresis requires a received signal transitioning from low to high exceed a particular level, e.g., 1/2 V.sub.DD, and which requires a signal transitioning from high to low to be lees than 1/2 V.sub.DD to turn off the detector circuit.
Thus, in normal operation, if an input signal applied to the circuit is of general magnitude of about 1/2 V.sub.DD, if the input circuit is constructed of a typical CMOS inverter, commonly both of the transistors of the inverter may be biased to conduct. This results in a relatively large current drawn through the device. When the current draw is multiplied across all of the input/output pins of the integrated circuit device, it can be appreciated that a relatively large current is required in the quiescent state of the integrated circuit device. This can be disadvantageous in many applications, such as video cameras/camcorders, lap top computers and the like which are battery operated and which require minimal use of the battery capacity for extended operation.
Typically, in the operation of the isolation circuit between two integrated circuits in delivering a signal from one integrated circuit device to another, if, for example, an output pulse is to be delivered extending beyond a single clock pulse, a high state is clocked from the output buffer of one integrated circuit at the clock pulse output. Thereafter, the output of the output buffer is tristated or switched to a high impedance state. The signal is detected by the input buffer circuit of the other integrated circuit, which switches to a high state. By virtue of the hysteresis effect of the input buffer circuit, the input buffer continues to report that a high state is being received, until the input signal drops below the threshold value, below 1/2 V.sub.DD, for example, as explained above.
Another of the problems that has been experienced with isolation circuits in the past is that typically isolation circuits have a limited noise immunity. In particular, isolation circuits do no generally permit a large margin of noise immunity because of the design requirement for an amount of hysteresis in the input buffer circuit. As a result, for example, if an input voltage is 1/2 V.sub.DD at an input pin, the difference is very small between the input potential and the threshold potential that must be exceeded for the circuit to change states. (The input would typically be at 1/2 V.sub.DD since the output of the transmitter or output buffer portion of the integrated circuit to which the circuit is connected is typically in a tristate impedance.) Consequently, if a noise spike or pulse is induced onto the input line, the magnitude of the pulse necessary to reach the switching threshold of the input buffer circuit is relatively small. A typical isolation circuit, for example, may provide noise immunity of only about 0.2 volts to about 0.8 volts, depending upon the particular variables of the circuit.
Another consideration in the design of the device interface circuits constructed according to the IEEE 1394-1995 standard is that of the propagation delay through the interface circuit. Typically, in the prior art, the propagation delay that is experienced is about two to three nanoseconds. In many applications, this propagation delay at least may need to be considered and, at worst, may disqualify the circuit for the particular application considered.
What was required, therefore, was a method and apparatus for providing a circuit and method for isolating dc or galvanic voltage between two or more circuits, such as integrated circuits or the like.
A circuit which is described in the above noted copending application minimized the above noted problems of the art prior thereto. This circuit provided an isolation circuit for providing dc isolation between two circuits that may be referenced to different ground potentials. The circuits to be isolated can be, for example, circuits on integrated circuit devices or the like. The isolation circuit includes an output buffer connected to deliver a signal to an output node of the circuit with which the output buffer is associated. An input buffer is connected to receive a signal delivered onto an input node. A capacitance, which may be a single capacitor or a combination of capacitors, is connected between the output and input nodes of each of the circuits. The input buffer includes a circuit for resisting a charge leakage from the capacitance, which, preferably, is a bus holder circuit or the like. If the circuits are provided on integrated circuits devices, the busholder may be provided either internally of externally to the integrated circuit devices. In another embodiment, a signal encoder may be associated with the input buffer to counteract or resist the effects of charge leakage from the capacitance, without the need for a bus holder or other charge holding circuit.
According to another aspect of the above noted pending application, an isolation circuit for providing dc isolation between first and second circuits is provided. The first and second circuits may be contained on integrated circuit devices or the like. The circuits may, but need not be, referenced to different ground potentials. The isolation circuit includes a transformer having first and second transformer coils. The first coil of the transformer is connected to a ground of the first circuit, and the second coil of the transformer is connected to a ground of the second circuit. A first capacitance, which may be single or multiple capacitors, may be connected between a signal input node of the second circuit and a second side of the second coil of the transformer. A signal output buffer is provided in the first circuit, and is connected to the output node. A signal input buffer is provided in the second circuit, connected to the respective input node, the signal input buffers being constructed to hold a desired state at the input node despite charge leakage from the capacitance. The signal input buffers may include, for example, bus hold circuits.
According to a still further aspect of the above noted copending application, a method is provided for providing dc isolation between a first circuit from a second circuit, which may be contained in separate integrated circuit devices in which a ground potential of the first circuit may be different from a ground potential of the second circuit. The method includes connecting a capacitance between respective signal input and output nodes of the first and second circuits. The capacitance may be provided on a single or multiple capacitor devices. A signal output buffer is contained in one of the circuits, being connected to an output node of the circuit on which it is contained, and a signal input buffer is contained in the other of the circuits, being connected to the input node of the circuit in which it is contained. The signal input buffers are constructed to hold a desired state at the input node despite charge leakage from the capacitance.
The step of providing a signal input buffer may be performed by providing a first inverter having an input connected to the input node and an output connected to the circuit, and providing a bus holder at the input to the inverter to hold a current state of the inverter despite charge leakage from the capacitor. The step of providing a bus holder may be performed by providing a second inverter across the first inverter in an opposite direction from the first inverter. The second inverter would typically have less output drive than the output buffer that is driving the input node.
According to yet another feature of the copending application, a method is presented for providing dc isolation between a first circuit and a second circuit. The circuits may be part of first and second integrated circuit devices, in which a ground potential of the first circuit may be different from a ground potential of the second circuit. The method includes connecting one side of a first coil of a transformer to a ground of the first circuit and one side of a second coil of the transformer to a ground of the second circuit. A first capacitance is connected between a signal output node of the first circuit and a second side of the first coil of the transformer. A second capacitance is connected between a signal input node of the second circuit and a second side of the second coil of the transformer. A signal output buffer is provided in the first circuit, connected to the output node. A signal input buffer is provided in the second circuit, connected to the input node. The signal input buffer is constructed to hold a desired state at an input of the circuit despite charge leakage from the capacitance.
The step of providing a signal input buffer may be performed by providing a first inverter having an input connected to the input node and an output connected to the circuit, and providing a bus holder at the input to the inverter to hold a current state of the inverter despite charge leakage from the capacitance. The bus holder may be provided by providing a second inverter across the first inverter in an opposite direction from the first inverter.
The circuit and method of the copending application result in the advantage that no differentiation logic is required to differentiate the driven signal. This reduces silicon device area. Moreover, only one external capacitor is required per lead for capacitive isolation, as opposed to a minimum of two external capacitors and seven external resistors used in a circuit complying with the capacitor embodiment of the IEEE 1394-1995 standard. For transformer isolation, only two external capacitors and one external transformer are required, as opposed to two external capacitors, one external transformer and a minimum of seven external resistors used in a circuit complying with the transformer embodiment of the IEEE 1394-1995 standard. This reduces components, board space and cost.
In addition, inputs swing rail-to-rail as opposed to 1/2 V.sub.DD. This increases noise margin. The inputs remain at the rails as opposed to normally sitting at 1/2 V.sub.DD. In the art prior thereto when the input remained at 1/2 V.sub.DD, the quiescent current draw could be very high, and careful design was required to ensure supply current did not exceed design limitations. In addition, the delay through the isolation barrier is much lower than in the art prior thereto. This reduces the timing constraints on both the physical layer and the link layer devices. The input circuit design constraints are much looser as opposed to critical threshold and hysteresis constraints in the art prior thereto.
However, none of the above described prior art solutions involve galvanic isolation of a system for an input with an internal pull-up as is commonly used in chip reset type inputs.